The disclosure relates to a method for forming fine patterns of a semiconductor device.
Due to the high degree of integration of semiconductor devices, the resolution required in semiconductor devices is smaller than the minimum resolution (1F) that can be resolved using photolithography equipment.
For example, when the minimum resolution that can be resolved by a single exposure process using the photolithography equipment is 45 nm, a semiconductor device requires a resolution smaller than 40 nm. (“Single exposure process” means an exposure process using one exposure mask.)
In order to overcome limits of the photolithography equipment, various patterning technologies have been developed and suggested.
Of these patterning technologies, double patterning technology divides patterns having a small pitch into two masks and repeating photo and etching processes twice using the two masks to obtain a desired target pattern.
FIG. 1 is a diagram illustrating an active region of a cell region 1000 and a peri/core region 2000 of a DRAM.
Referring to FIG. 1, when it is impossible to form a pattern having a small pitch as shown in A and a space between island patterns as shown in B, which is below a specific space, by a single exposure method using one mask, a conventional double patterning method is performed to divide patterns (the target patterns) of FIG. 1 into two masks and to pattern using the two masks, thereby obtaining a target pattern.
The conventional double patterning method comprises repeating an exposing process twice using two masks, so that an actual pattern has a different size from that of the target pattern depending on mis-alignment of exposure equipment and process change.